1. Field of the Invention
The present invention relates to memory systems used in digital processing systems, and more specifically to a method and apparatus which enables a memory access system to provide increased throughput rates while accessing large volumes of data.
2. Related Art
Memory access systems are generally employed to access (store/retrieve) data in/from a memory. Large volumes (e.g., of the order of kilo or Mega-bytes) of data are often retrieved from memories. For example, software instructions may need to be retrieved from a large external memory to a smaller on-chip internal memory, prior to execution of the instructions. Such an approach enables operation using a faster (but smaller, and thus not-too expensive) on-chip memory, as is well known in the relevant arts.
One variable of interest while accessing such large volume of data is the throughput rate (number of bytes transferred per unit time) at which data transfer is performed. Often it is desirable that the throughput rates be high such that data transfer can be completed within a certain duration. For example, in the above noted illustrative example, the memories may be employed associated with real-time systems in which real-time data needs to be processed quickly by executing the software instructions, and lower throughput rates in transfer (of software instructions) may lead to software instructions not being timely available for execution. Several undesirable consequences such as loss of data and/or appropriate action not being taken in a timely manner, may result when the software instructions are not timely available.
One configuration in which enhancement of throughput rate is of particular interest is in which a memory access system contains several sub-delays in the data transfer path (with each sub-system potentially causing potentially large delays), and the data units (forming the large of data of interest) are retrieved and stored sequentially without pipelining (i.e., overlap on a time scale). The high delays may be introduced, for example, due to sharing of common resources. As an illustration, a single interface may be used associated with accessing multiple memories (or other sub-systems), and requests to all such memories may need to be channeled through that single interface.
Thus, high delays (and thus lower throughput rates) may be caused due to arbitration (determining which access gets priority), queuing (waiting while the present and/or higher priority accesses get served), etc., for a shared resource. The effective throughput rate in such a scenario is inversely proportional to the sum of the sub-delays. The throughput rate may be lower than a desired rate due to the high sub-delays. At least for reasons such as those noted above, it may be desirable to increase the throughput rate.
Several prior approaches are known to attempt to increase the throughput rate in a memory access system. In one prior approach, a processor (e.g., a central processing unit) may merely need to specify the specific block of data to be transferred from a source memory to a destination memory, and a direct memory access (DMA) engine may complete such transfer without requiring substantial additional intervention of the processor. The transfer may be completed quickly as the processor may not now be a bottleneck (in effecting the transfer). However, it may be desirable to further increase the data throughput rate.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.